Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

As the size of CMOS devices is scaled down to lower the power consumption and space occupied on the chip to the nano-scale, unfortunately, noise is not reduced accordingly. As a result, interference due to noise can significantly affect circuit performance and operation. Since noises are random and dynamic in nature, probabilistic noise-tolerant approaches are more desirable to handle this problem. However, trade-offs between hardware complexity and noise-tolerance are severe design challenges in the probabilistic-based noise-tolerant approaches. In this paper, we proposed a cost-effective common-feedback probabilistic-based noise-tolerant VLSI circuit based on Markov random field (MRF) theory. We proposed a common latch feedback method to lower the hardware complexity. To further enhance the noise-tolerant ability, the common latch feedback technique is combined with Schmitt trigger. To demonstrate the proof-of-concept design, a 16-bit carry-lookahead adder was implemented in the TSMC 90 nm CMOS process technology. As compared with the state-of-art master-and-slave MRF design, the experimental results show that not only the transistor count can be saved by 20%, the noise-tolerant performance can also be enhanced from 18.1 dB to 24.2 dB in the proposed common feedback MRF design.