Hardware-efficient multi-standard video transform core

This study presents a unified hybrid architecture to compute the inverse discrete cosine transform (IDCT) of multiple modern video decoders such as moving picture experts group (MPEG-4), H.264, VC-1 and high efficiency video coding (HEVC). The proposed hardware sharing architecture requires a lower hardware cost than that for individual implementations, and maximizes the proportion of the circuit that is reused during the computation. The proposed architecture design needs only adders and shifters to significantly reduce the hardware cost. Thus, the resource sharing method can increase the circuit sharing capability and achieve high hardware efficiency. For verification, a TSMC 0.18-μm CMOS process is applied to implement the IDCT chip, and the maximum throughput rate of the proposed design is 1000 MP/s with a hardware cost of 16.5 k gates.