Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

Huang Chang Lee; Chung Chao Cheng; Yeong Luh Ueng

doi:10.1109/ISTC.2014.6955094

Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

Huang Chang Lee^*, Chung Chao Cheng, Yeong Luh Ueng

^*Corresponding author for this work

National Tsing Hua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.

Original language	English
Title of host publication	International Symposium on Turbo Codes and Iterative Information Processing, ISTC
Publisher	IEEE Computer Society
Pages	102-106
Number of pages	5
ISBN (Electronic)	9781479959853
DOIs	https://doi.org/10.1109/ISTC.2014.6955094
State	Published - 12 11 2014
Externally published	Yes
Event	2014 8th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2014 - Bremen, Germany Duration: 18 08 2014 → 22 08 2014

Publication series

Name	International Symposium on Turbo Codes and Iterative Information Processing, ISTC
ISSN (Print)	2165-4700
ISSN (Electronic)	2165-4719

Conference

Conference	2014 8th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2014
Country/Territory	Germany
City	Bremen
Period	18/08/14 → 22/08/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

High-throughput Decoder
Low-density Parity-check (LDPC) Codes
Min-Sum Algorithm

Access to Document

10.1109/ISTC.2014.6955094

Cite this

Lee, H. C., Cheng, C. C., & Ueng, Y. L. (2014). Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders. In International Symposium on Turbo Codes and Iterative Information Processing, ISTC (pp. 102-106). Article 6955094 (International Symposium on Turbo Codes and Iterative Information Processing, ISTC). IEEE Computer Society. https://doi.org/10.1109/ISTC.2014.6955094

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title = "Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders",

abstract = "In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.",

keywords = "High-throughput Decoder, Low-density Parity-check (LDPC) Codes, Min-Sum Algorithm",

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note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 8th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2014 ; Conference date: 18-08-2014 Through 22-08-2014",

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doi = "10.1109/ISTC.2014.6955094",

language = "英语",

series = "International Symposium on Turbo Codes and Iterative Information Processing, ISTC",

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Lee, HC, Cheng, CC & Ueng, YL 2014, Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders. in International Symposium on Turbo Codes and Iterative Information Processing, ISTC., 6955094, International Symposium on Turbo Codes and Iterative Information Processing, ISTC, IEEE Computer Society, pp. 102-106, 2014 8th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2014, Bremen, Germany, 18/08/14. https://doi.org/10.1109/ISTC.2014.6955094

Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders. / Lee, Huang Chang; Cheng, Chung Chao; Ueng, Yeong Luh.
International Symposium on Turbo Codes and Iterative Information Processing, ISTC. IEEE Computer Society, 2014. p. 102-106 6955094 (International Symposium on Turbo Codes and Iterative Information Processing, ISTC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Cheng, Chung Chao

AU - Ueng, Yeong Luh

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N2 - In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.

AB - In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.

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Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

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