Abstract
This paper designs an optimized hardware generator (IP Generator) based on convolutional neural networks. Users can use IP Generator to create any hardware architectures for neural network model they want. By the efficient user interface, the IP generator can output the architecture. You can get the corresponding optimized Verilog code efficiently. The network is a network model that simplifies some network layers by Yolo-v1. It can run 100MHz on Xilinx ZCU102 board which can reach 28.8GOP/s.
| Original language | English |
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| Title of host publication | 2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781665433280 |
| DOIs | |
| State | Published - 2021 |
| Externally published | Yes |
| Event | 8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 - Penghu, Taiwan Duration: 15 09 2021 → 17 09 2021 |
Publication series
| Name | 2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 |
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Conference
| Conference | 8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 |
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| Country/Territory | Taiwan |
| City | Penghu |
| Period | 15/09/21 → 17/09/21 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
Keywords
- Convolution Neural Networks(CNNs)
- IP Generators (Automatic Verilog Generators)