Hardware implementation for a genetic algorithm

Pei Yin Chen; Ren Der Chen; Yu Pin Chang; Leang San Shieh; H. A. Malki

doi:10.1109/TIM.2007.913807

Hardware implementation for a genetic algorithm

Pei Yin Chen^*, Ren Der Chen, Yu Pin Chang, Leang San Shieh, H. A. Malki

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

34 Scopus citations

Abstract

A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.

Original language	English
Pages (from-to)	699-705
Number of pages	7
Journal	IEEE Transactions on Instrumentation and Measurement
Volume	57
Issue number	4
DOIs	https://doi.org/10.1109/TIM.2007.913807
State	Published - 04 2008
Externally published	Yes

Keywords

Field-programmable gate array (FPGA)
Genetic algorithm (GA)
Intellectual property (IP)
Software system
Verilog

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10.1109/TIM.2007.913807

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AU - Shieh, Leang San

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KW - Intellectual property (IP)

KW - Software system

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Hardware implementation for a genetic algorithm

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Keywords

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