TY - GEN
T1 - Hardware implementation for real-time 3D rendering in 2D-to-3D conversion
AU - Lai, Yeong Kang
AU - Chung, Yu Chieh
AU - Lai, Yu Fan
PY - 2013
Y1 - 2013
N2 - With the advances in central processing unit (CPU) capability, 3D display technology becomes popular in recent years. Now, there are more and more 3D products such as 3D camera, 3D projector, and 3D-TV. The 3D technology is not difficult to understand because most of the video contents are captured through two individual lenses. The corresponding video contents are considered as two respective bit streams. However, how to transform traditional 2D video contents to 3D one is a critical problem to solve it. This paper proposes a realtime 3D rendering architecture for view synthesis in 2D-to-3D conversion. The real-time architecture can support 60 frames per second and full HD resolution (1920×1080) on FPGA platform.
AB - With the advances in central processing unit (CPU) capability, 3D display technology becomes popular in recent years. Now, there are more and more 3D products such as 3D camera, 3D projector, and 3D-TV. The 3D technology is not difficult to understand because most of the video contents are captured through two individual lenses. The corresponding video contents are considered as two respective bit streams. However, how to transform traditional 2D video contents to 3D one is a critical problem to solve it. This paper proposes a realtime 3D rendering architecture for view synthesis in 2D-to-3D conversion. The real-time architecture can support 60 frames per second and full HD resolution (1920×1080) on FPGA platform.
UR - http://www.scopus.com/inward/record.url?scp=84883352412&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2013.6571991
DO - 10.1109/ISCAS.2013.6571991
M3 - 会议稿件
AN - SCOPUS:84883352412
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 893
EP - 896
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -