Abstract
In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations.
Original language | English |
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Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 185-188 |
Number of pages | 4 |
ISBN (Electronic) | 078035012X |
DOIs | |
State | Published - 1999 |
Externally published | Yes |
Event | 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong Duration: 18 01 1999 → 21 01 1999 |
Publication series
Name | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
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Volume | 1999-January |
Conference
Conference | 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 |
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Country/Territory | Hong Kong |
City | Wanchai |
Period | 18/01/99 → 21/01/99 |
Bibliographical note
Publisher Copyright:© 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.