Abstract
This letter presents high-linearity 0.13-μm CMOS devices based on field-plate technology. The field-plate technology reduces the electric field between the gate and drain terminals, subsequently forming a field-plate-induced depletion region and reducing the leakage current to significantly improve linearity and power of the CMOS devices. The third-order intermodulation product of 0.13-μm NMOS devices with and without field-plate technology are -41.8 and -32.4 dBm, respectively, for input power of -10 dBm. Experimental results indicate that the field-plate architecture exhibits high linearity and power for CMOS RFIC applications.
Original language | English |
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Pages (from-to) | 843-845 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 27 |
Issue number | 10 |
DOIs | |
State | Published - 2006 |
Keywords
- 0.13-μm RFCMOS
- Drain-induced barrier lowering (DIBL)
- Fieldplate technology
- Linearity