High-linearity performance of 0.13-μm CMOS devices using field-plate technology

Chien Cheng Wei*, Hsien Chin Chiu, Wu Shiung Feng

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

7 Scopus citations

Abstract

This letter presents high-linearity 0.13-μm CMOS devices based on field-plate technology. The field-plate technology reduces the electric field between the gate and drain terminals, subsequently forming a field-plate-induced depletion region and reducing the leakage current to significantly improve linearity and power of the CMOS devices. The third-order intermodulation product of 0.13-μm NMOS devices with and without field-plate technology are -41.8 and -32.4 dBm, respectively, for input power of -10 dBm. Experimental results indicate that the field-plate architecture exhibits high linearity and power for CMOS RFIC applications.

Original languageEnglish
Pages (from-to)843-845
Number of pages3
JournalIEEE Electron Device Letters
Volume27
Issue number10
DOIs
StatePublished - 2006

Keywords

  • 0.13-μm RFCMOS
  • Drain-induced barrier lowering (DIBL)
  • Fieldplate technology
  • Linearity

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