@inproceedings{6ab1b10089fc4b3ea0bfbd988e0af7b8,
title = "High linearity performance of 0.13 μm CMOS devices using field-plate technology",
abstract = "High linearity performance of 0.13 μm CMOS devices using field-plate technology is presented in this paper. The field-plate technology functions for reducing the electric field between gate and drain terminals, which provides a field-plate induced depletion region and decreases the leakage current to greatly improve the linearity and power performance of CMOS devices. The third-order inter-modulation product (IM3) of 0.13 μm NMOS devices with and without field-plate technology are -41.8 dBm and -32.4 dBm for input power is -10 dBm, respectively. The experimental results show that the field-plate architecture is more effective to exhibit high linearity and power for CMOS RFIC applications.",
keywords = "130nm CMOS, Field-plate technology, High linearity",
author = "Wei, {Chien Cheng} and Chiu, {Hsien Chin} and Feng, {Wu Shiung}",
year = "2006",
language = "英语",
isbn = "0780395727",
series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",
pages = "474--477",
booktitle = "2006 IEEE Radio Frequency Integrated Circuits(RFIC) Symposium - Digest of Papers",
note = "2006 IEEE Radio Frequency Integrated Circuits Symposium ; Conference date: 11-06-2006 Through 13-06-2006",
}