High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

Tung Ming Pan; Chih Jen Chang

doi:10.1088/0268-1242/26/7/075004

High-performance poly-silicon TFTs with high-k Y₂O₃ gate dielectrics

Tung Ming Pan^*, Chih Jen Chang

^*Corresponding author for this work

Department of Electronic Engineering

Chang Gung University

Research output: Contribution to journal › Journal Article › peer-review

22 Scopus citations

Abstract

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y₂O₃ gate dielectric for different annealing times. The high-k Y₂O₃ poly-Si TFT device annealed in O₂ gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm ² V^-1 s^-1, small subthreshold slope of 269 mV dec^-1, and high I_on/I_off current ratio of 1.83 × 10⁷. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y₂O ₃/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y₂O₃ TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

Original language	English
Article number	075004
Journal	Semiconductor Science and Technology
Volume	26
Issue number	7
DOIs	https://doi.org/10.1088/0268-1242/26/7/075004
State	Published - 07 07 2011

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title = "High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics",

abstract = "In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.",

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T1 - High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

AU - Pan, Tung Ming

AU - Chang, Chih Jen

PY - 2011/7/7

Y1 - 2011/7/7

N2 - In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

AB - In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

UR - https://www.scopus.com/pages/publications/79953837368

U2 - 10.1088/0268-1242/26/7/075004

DO - 10.1088/0268-1242/26/7/075004

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SN - 0268-1242

VL - 26

JO - Semiconductor Science and Technology

JF - Semiconductor Science and Technology

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ER -

High-performance poly-silicon TFTs with high-k Y₂O₃ gate dielectrics

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