High speed pipelined booth multiplier

A new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. Then, a low voltage; high speed pipelined modified Booth multiplier architecture is first presented in 3.3V, 1GHz. This proposed pipelined Booth multiplier can reduce the delay time of critical path by levelizing the complex gate in the MBE decoder to overcome the speed bottleneck of pipelined booth multiplier, and the speed improvement is up to 66.3 percent. Moreover, a new Manchester carry-bypass adder (MCBA) is proposed for the high speed, low latency pipelined Booth multiplier. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the highest operating frequency can be up to 1.20GHz and speed bottleneck is overcome with 40.16 percent improvement. The average energy consumption in the new MCBA is only 16.81 uw per MHz. with 30.59 percent improvement. The 13-bit new MCBA is pipelined into 2 stages with worst-case delay of 0.833ns and consumes only 16.81mw. The average power consumption of the proposed low latency pipelined Booth multiplier is only 60.18mw and the total transistor count of whole multiplier is 3287.