High throughput DA-based DCT with high accuracy error-compensated adder tree

Yuan Ho Chen; Tsin Yuan Chang; Chung Yi Li

doi:10.1109/TVLSI.2009.2037968

High throughput DA-based DCT with high accuracy error-compensated adder tree

Yuan Ho Chen^*, Tsin Yuan Chang, Chung Yi Li

^*Corresponding author for this work

National Tsing Hua University

Research output: Contribution to journal › Journal Article › peer-review

29 Scopus citations

Abstract

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise- ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

Original language	English
Article number	5378487
Pages (from-to)	709-714
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2009.2037968
State	Published - 04 2011
Externally published	Yes

Keywords

2-D discrete cosine transform (DCT)
Distributed arithmetic (DA)-based
error-compensated adder-tree (ECAT)

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10.1109/TVLSI.2009.2037968

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@article{3040876b06d5469db1ce2225606453ab,

title = "High throughput DA-based DCT with high accuracy error-compensated adder tree",

abstract = "In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise- ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.",

keywords = "2-D discrete cosine transform (DCT), Distributed arithmetic (DA)-based, error-compensated adder-tree (ECAT)",

author = "Chen, {Yuan Ho} and Chang, {Tsin Yuan} and Li, {Chung Yi}",

year = "2011",

month = apr,

doi = "10.1109/TVLSI.2009.2037968",

language = "英语",

volume = "19",

pages = "709--714",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - High throughput DA-based DCT with high accuracy error-compensated adder tree

AU - Chen, Yuan Ho

AU - Chang, Tsin Yuan

AU - Li, Chung Yi

PY - 2011/4

Y1 - 2011/4

N2 - In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise- ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

AB - In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise- ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

KW - 2-D discrete cosine transform (DCT)

KW - Distributed arithmetic (DA)-based

KW - error-compensated adder-tree (ECAT)

UR - http://www.scopus.com/inward/record.url?scp=79953100923&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2009.2037968

DO - 10.1109/TVLSI.2009.2037968

M3 - 文章

AN - SCOPUS:79953100923

SN - 1063-8210

VL - 19

SP - 709

EP - 714

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

M1 - 5378487

ER -

High throughput DA-based DCT with high accuracy error-compensated adder tree

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