High throughput DA-based DCT with high accuracy error-compensated adder tree

Yuan Ho Chen*, Tsin Yuan Chang, Chung Yi Li

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

29 Scopus citations


In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise- ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

Original languageEnglish
Article number5378487
Pages (from-to)709-714
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
StatePublished - 04 2011
Externally publishedYes


  • 2-D discrete cosine transform (DCT)
  • Distributed arithmetic (DA)-based
  • error-compensated adder-tree (ECAT)


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