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Highly scalable NAND-type PHINES flash memory for data flash applications

  • C. C. Yeh*
  • , Y. Y. Liao
  • , W. J. Tsai
  • , T. C. Lu
  • , T. F. Ou
  • , H. L. Kao
  • , Tahui Wang
  • , Wen Chi Ting
  • , Joseph Ku
  • , Chih Yuau Lu
  • *Corresponding author for this work
  • Macronix International Co., Ltd. Taiwan
  • National Yang Ming Chiao Tung University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, two NAND-type PHINES flash memory architectures (1 bit/cell and physically 2 bit/cell) are proposed for mass storage applications. PHINES nitride trapping storage flash memory features high storage density, low power operation, good reliability, simple process, and high programming throughput. Fifteen-nm generation is feasible for future flash memory technology.

Original languageEnglish
Title of host publication21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Pages76-77
Number of pages2
DOIs
StatePublished - 2006
Externally publishedYes
Event21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006 - Monteray, CA, United States
Duration: 12 02 200616 02 2006

Publication series

Name21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Volume2006

Conference

Conference21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Country/TerritoryUnited States
CityMonteray, CA
Period12/02/0616/02/06

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