Hot-carrier reliability of power SOI EDNMOS

In this paper, hot-carrier-induced degradation test is performed on the 100 V power silicon-on-insulator n-type extended drain MOSFET with shallow trench isolation structure at the maximum substrate current condition under dc bias stress. Double reduced surface field design is employed to make sure the capability of the device is over 100 V. The degradation parameters including drain current, maximum transconductance, threshold voltage and the peak value of the substrate current are investigated, according to Joint Electron Devices Engineering Council Standard. Abnormal degradation of the linear and less than perfect linear degradation of the saturation are observed and they are attributed to the presence of two different hot-carrier injection sites in the device. Technology computer-aided design simulation tool is employed to provide the explanations in this paper.