IC HTOL test stress condition optimization

Brian Peng, Ing Yi Chen, Sy Yen Kuo, Colin Bolger

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

15 Scopus citations

Abstract

HTOL (High Temperature Operation Life) test is used to determine the effects of bias and temperature stress conditions on solid-state devices over time. It simulates the devices' operating condition in an accelerated manner, and is primarily for device reliability evaluation. This paper addresses an SA (Simulated Annealing) method used for the HTOL test stress condition decision-making that is an optimization problem. The goal is to reduce the resources for the HTOL test, hardware or time, under reliability constraints. The theory of reliability statistic model and the SA algorithm are presented. In our optimization algorithm, we need to calculate the accurate HTOL stressed power for the next optimization loop since the Vs (Stressed Voltage) that is optimized will affect not only Afv (Voltage Acceleration Factor) but also Aft (Thermal Acceleration Factor). A curve-fitting algorithm is applied to get reasonable accelerated factors and reliability calculations. The model selection process and statistical analysis of fitted data by different models are also presented. Experimental results with different stress condition priorities and different user settings are given to demonstrate the effectiveness of our approach.

Original languageEnglish
Title of host publicationProceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
EditorsR. Aitken, A. Salsano, R. Velazco, X. Sun
Pages272-279
Number of pages8
DOIs
StatePublished - 2004
Externally publishedYes
Event19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Cannes, France
Duration: 10 10 200413 10 2004

Publication series

NameIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/TerritoryFrance
CityCannes
Period10/10/0413/10/04

Fingerprint

Dive into the research topics of 'IC HTOL test stress condition optimization'. Together they form a unique fingerprint.

Cite this