Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias

Minchen Chang*, Jengping Lin, Steven N. Shih, Tieh Chiang Wu, Brady Huang, Jen Yang, Pei Ing Lee

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

43 Scopus citations

Abstract

A negative wordline bias scheme is utilized to reduce the subthreshold leakage of deep submicron DRAM cell transistors. With excessive negative wordline bias, gate-induced drain leakage (GIDL) could dominate cell leakage and degrade product retention time performance. The dependence of retention time on negative wordline bias for a 256-Mbit DRAM with 0.14 μm ground rule is investigated. The retention fail bit count in the tail distribution increases as wordline bias goes more negative and as temperature increases. A cell array with a density of 1.14M is also characterized for the device leakage behavior. The negative wordline bias and temperature dependent GIDL is believed to be due to band to defect tunneling. Hence, elimination of traps near the oxide/silicon interface in the gate to drain overlap region during the DRAM fabrication process is important for the negative wordline scheme.

Original languageEnglish
Pages (from-to)1036-1041
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume50
Issue number4
DOIs
StatePublished - 04 2003

Keywords

  • Gate-induced drain leakage (GIDL)
  • Negative wordline
  • Retention time

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