Impact of High-K Offset Spacer in 65-nm Node SOI Devices

In this letter, 65-nm node silicon-on-insulator devices with high-k offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k offset spacer dielectric can effectively increase the ON-state driving current I_on and reduce the off leakage current ioffdue to the high vertical fringing electric field effect. This fringing field can significantly improve the ion/ioffcurrent ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.