Abstract
In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (G_m max) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (V BG) operation mode, theV BGcan provide a wide threshold voltage (V TH) tuning range 2 V when theV BGis modulated from 0 to -4 V. The negativeV BGbias stress would induce electron injection from the BG, resulting in positiveV THshift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negativeV BGstress, usingV BGto modulate theV THof the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independentV BGto adjust theV THof the JL-TFTs to meet the multiple-V THrequirement of advanced integrated circuits.
| Original language | English |
|---|---|
| Pages (from-to) | 6171-6176 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 68 |
| Issue number | 12 |
| DOIs | |
| State | Published - 01 12 2021 |
| Externally published | Yes |
Bibliographical note
Publisher Copyright:© 1963-2012 IEEE.
Keywords
- Dual-gate (DG)
- junctionless (JL) transistor
- nanosheet (NSH) channel
- reliability
- thin-film transistor (TFT)