Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters

Srinivas Gude; Chia Chi Chu

doi:10.1109/IAS.2018.8544567

Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters

Srinivas Gude
, Chia Chi Chu

National Tsing Hua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The estimation of phase-angle, frequency and amplitude are crucial for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (lP-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities respectively. However, under the presence of harmonics, unbalance and dc offsets, the estimated quantities by these EPLLs may contain periodic ripples. Therefore in order to eliminate these periodic ripples multiple delayed signal cancellation (MDSC) filters are placed in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally and compared with recent advanced EPLLs.

Original language	English
Title of host publication	2018 IEEE Industry Applications Society Annual Meeting, IAS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538645369
DOIs	https://doi.org/10.1109/IAS.2018.8544567
State	Published - 26 11 2018
Externally published	Yes
Event	2018 IEEE Industry Applications Society Annual Meeting, IAS 2018 - Portland, United States Duration: 23 09 2018 → 27 09 2018

Publication series

Name	2018 IEEE Industry Applications Society Annual Meeting, IAS 2018

Conference

Conference	2018 IEEE Industry Applications Society Annual Meeting, IAS 2018
Country/Territory	United States
City	Portland
Period	23/09/18 → 27/09/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE

Keywords

Amplitude
Enhanced phase-locked loops (EPLLs)
Frequency
Multiple delayed signal cancellation (MDSC)
Phase-angle
Proportional-integral-derivative (PID) controller

Access to Document

10.1109/IAS.2018.8544567

Cite this

Gude, S., & Chu, C. C. (2018). Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters. In 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018 Article 8544567 (2018 IEEE Industry Applications Society Annual Meeting, IAS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IAS.2018.8544567

@inproceedings{23165a3645ce431798a62c63031bc149,

title = "Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters",

abstract = "The estimation of phase-angle, frequency and amplitude are crucial for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (lP-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities respectively. However, under the presence of harmonics, unbalance and dc offsets, the estimated quantities by these EPLLs may contain periodic ripples. Therefore in order to eliminate these periodic ripples multiple delayed signal cancellation (MDSC) filters are placed in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally and compared with recent advanced EPLLs.",

keywords = "Amplitude, Enhanced phase-locked loops (EPLLs), Frequency, Multiple delayed signal cancellation (MDSC), Phase-angle, Proportional-integral-derivative (PID) controller",

author = "Srinivas Gude and Chu, \{Chia Chi\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE; 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018 ; Conference date: 23-09-2018 Through 27-09-2018",

year = "2018",

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day = "26",

doi = "10.1109/IAS.2018.8544567",

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Gude, S & Chu, CC 2018, Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters. in 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018., 8544567, 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018, Portland, United States, 23/09/18. https://doi.org/10.1109/IAS.2018.8544567

Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters. / Gude, Srinivas; Chu, Chia Chi.
2018 IEEE Industry Applications Society Annual Meeting, IAS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8544567 (2018 IEEE Industry Applications Society Annual Meeting, IAS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chu, Chia Chi

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Y1 - 2018/11/26

N2 - The estimation of phase-angle, frequency and amplitude are crucial for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (lP-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities respectively. However, under the presence of harmonics, unbalance and dc offsets, the estimated quantities by these EPLLs may contain periodic ripples. Therefore in order to eliminate these periodic ripples multiple delayed signal cancellation (MDSC) filters are placed in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally and compared with recent advanced EPLLs.

AB - The estimation of phase-angle, frequency and amplitude are crucial for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (lP-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities respectively. However, under the presence of harmonics, unbalance and dc offsets, the estimated quantities by these EPLLs may contain periodic ripples. Therefore in order to eliminate these periodic ripples multiple delayed signal cancellation (MDSC) filters are placed in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally and compared with recent advanced EPLLs.

KW - Amplitude

KW - Enhanced phase-locked loops (EPLLs)

KW - Frequency

KW - Multiple delayed signal cancellation (MDSC)

KW - Phase-angle

KW - Proportional-integral-derivative (PID) controller

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T2 - 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018

Y2 - 23 September 2018 through 27 September 2018

ER -

Gude S, Chu CC. Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters. In 2018 IEEE Industry Applications Society Annual Meeting, IAS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8544567. (2018 IEEE Industry Applications Society Annual Meeting, IAS 2018). doi: 10.1109/IAS.2018.8544567

Improved performance of single-phase and two-phase enhanced phase-locked loops by using multiple delayed signal cancellation filters

Abstract

Publication series

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Bibliographical note

Keywords

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