Improvement in radiation-hard CMOS logic gates for noise margin

S. J. Yih; M. L. Chang; J. G. Hwu; W. S. Feng

Improvement in radiation-hard CMOS logic gates for noise margin

S. J. Yih^*
, M. L. Chang
, J. G. Hwu
, W. S. Feng

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage V_DD.

Original language	English
Pages (from-to)	1916-1919
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 09 06 1997 → 12 06 1997

Cite this

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title = "Improvement in radiation-hard CMOS logic gates for noise margin",

abstract = "A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage VDD.",

author = "Yih, \{S. J.\} and Chang, \{M. L.\} and Hwu, \{J. G.\} and Feng, \{W. S.\}",

year = "1997",

language = "英语",

volume = "3",

pages = "1916--1919",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

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note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

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T1 - Improvement in radiation-hard CMOS logic gates for noise margin

AU - Yih, S. J.

AU - Chang, M. L.

AU - Hwu, J. G.

AU - Feng, W. S.

PY - 1997

Y1 - 1997

N2 - A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage VDD.

AB - A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage VDD.

UR - https://www.scopus.com/pages/publications/0030648301

M3 - 会议文章

AN - SCOPUS:0030648301

SN - 0271-4310

VL - 3

SP - 1916

EP - 1919

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Improvement in radiation-hard CMOS logic gates for noise margin

Abstract

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