Infrastructure development and integration of electrical-based dimensional process window checking

Kelvin Yih Yuh Doong*, Jurcy Cho Hsi Huang, Chia Chi Chu, Sheng Che Lin, Lien Jung Hung, Susan Pei Shan Ho, Sunnys Hsieh, Robin Chien Jung Wang, Philip Chia Chi Lin, Roger Wen Lung Kang, Konrad L. Young

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

8 Scopus citations


This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchical test vehicle design flow from the design of the test structure to the analysis of the electrical test data. Symbolic parameter representation is adopted to describe the relationship between design rules and test structure parameters. This integrated infrastructure also provides a specific capability for controlling local/global layout geometry and pattern density, thereby fulfilling deep sub-micron design criteria. With the aid of this design platform, discrepancies between the design rule set, test structure design, and the testing plan are minimized. Using the function-independent Test Structure Design Intellectual Property (TSD-IP) provided by this infrastructure, the process-window is quantitatively characterized as the electrical parameters. A cross-generation test vehicle (130-nm/90-nm nodes), used for evaluating any overlay shifts and variations in critical dimensions across the intra- and interphoto fields, has been developed to demonstrate the proposed design infrastructure.

Original languageEnglish
Pages (from-to)123-141
Number of pages19
JournalIEEE Transactions on Semiconductor Manufacturing
Issue number2
StatePublished - 05 2004
Externally publishedYes


  • Automatic test equipment
  • Design automation
  • Full-loop process
  • Integrated circuit layout
  • Short-loop process


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