Integrated-circuit reliability simulation including dynamic stress effects

Wen Jay Hsu*, Sudhir M. Gowda, Bing J. Sheu, Chang Gyu Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The development of high-reliability integrated circuits requires accurate prediction of circuit lifetime including dynamic stress effects. A systematic approach for classifying dynamic stress conditions and accounting for AC-induced excessive hot-carrier damage using an effective degradation factor is described. An equivalent DC degradation monitor is simulated using a two-pass approach. Experimental results on digital circuits, including memory circuits, are presented. In particular, results are presented on substrate currents in NAND gates, degradation in precharging current, and a SRAM cell and peripheral circuits.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780300157
StatePublished - 1991
Externally publishedYes
EventProceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 12 05 199115 05 1991

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the IEEE 1991 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period12/05/9115/05/91

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