Integrated FPGA based ASIC design on error code correction counter for UPS telecommunication

Jian Long Kuo*, Chin Chin Tsai, L. F. Lai, T. J. Chen, T. W. Ding

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

Abstract

The paper presents a hybrid error code correction counter suitable for the UPS telecommunication with three different signal specifications. Based on the FPGA implementation, the required functional blocks can be partitioned and designed as follows: pulse combination, serial to parallel data transfer, one frame latching, combination logic to serial pulse generation, MPU based one second pulse generation, asynchronous counter with asynchronous clear. Through systematic integration as described in this paper, the error code correction counter can be successfully designed. It is believed that the associated implementation technique will be applicable to the research and development of the tester technology on the UPS telecommunication.

Original languageEnglish
Pages512-516
Number of pages5
StatePublished - 2001
Event4th IEEE International Conference on Power Electronics and Drive Systems - Denpasar, Bali, Indonesia
Duration: 22 10 200125 10 2001

Conference

Conference4th IEEE International Conference on Power Electronics and Drive Systems
Country/TerritoryIndonesia
CityDenpasar, Bali
Period22/10/0125/10/01

Keywords

  • Digital ASIC design
  • Error code correction counter (ECC)
  • FPGA
  • UPS telecommunication

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