Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

Shian Jyh Lin; Chao Sung Lai; Sheng Tsung Chen; Yi Jung Chen; Brady Huang; Neng Tai Shih; Chung Yuan Lee; Pei Ing Lee

doi:10.1109/VTSA.2008.4530817

Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

Shian Jyh Lin^*
, Chao Sung Lai
, Sheng Tsung Chen
, Yi Jung Chen
, Brady Huang
, Neng Tai Shih
, Chung Yuan Lee
, Pei Ing Lee

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%, 15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ioff) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll-off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.

Original language	English
Title of host publication	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages	99-100
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2008.4530817
State	Published - 2008
Event	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan Duration: 21 04 2008 → 23 04 2008

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Country/Territory	Taiwan
City	Hsinchu
Period	21/04/08 → 23/04/08

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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10.1109/VTSA.2008.4530817

Cite this

Lin, S. J., Lai, C. S., Chen, S. T., Chen, Y. J., Huang, B., Shih, N. T., Lee, C. Y., & Lee, P. I. (2008). Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing. In 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA (pp. 99-100). Article 4530817 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2008.4530817

@inproceedings{ad718471233c4c71a7176e1e728a33a7,

title = "Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing",

abstract = "We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5\%, 15\%, and 39\% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ioff) gains 4.3\% and 11.8\% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150\% and 500\% respectively. Vt roll-off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.",

author = "Lin, \{Shian Jyh\} and Lai, \{Chao Sung\} and Chen, \{Sheng Tsung\} and Chen, \{Yi Jung\} and Brady Huang and Shih, \{Neng Tai\} and Lee, \{Chung Yuan\} and Lee, \{Pei Ing\}",

year = "2008",

doi = "10.1109/VTSA.2008.4530817",

language = "英语",

isbn = "9781424416158",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

pages = "99--100",

booktitle = "2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA",

note = "2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA ; Conference date: 21-04-2008 Through 23-04-2008",

}

Lin, SJ, Lai, CS, Chen, ST, Chen, YJ, Huang, B, Shih, NT, Lee, CY & Lee, PI 2008, Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing. in 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA., 4530817, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, pp. 99-100, 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, Hsinchu, Taiwan, 21/04/08. https://doi.org/10.1109/VTSA.2008.4530817

Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing. / Lin, Shian Jyh; Lai, Chao Sung; Chen, Sheng Tsung et al.
2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA. 2008. p. 99-100 4530817 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

AU - Lin, Shian Jyh

AU - Lai, Chao Sung

AU - Chen, Sheng Tsung

AU - Chen, Yi Jung

AU - Huang, Brady

AU - Shih, Neng Tai

AU - Lee, Chung Yuan

AU - Lee, Pei Ing

PY - 2008

Y1 - 2008

N2 - We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%, 15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ioff) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll-off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.

AB - We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%, 15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ioff) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll-off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.

UR - https://www.scopus.com/pages/publications/49049119276

U2 - 10.1109/VTSA.2008.4530817

DO - 10.1109/VTSA.2008.4530817

M3 - 会议稿件

AN - SCOPUS:49049119276

SN - 9781424416158

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SP - 99

EP - 100

BT - 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA

T2 - 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA

Y2 - 21 April 2008 through 23 April 2008

ER -

Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

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