Investigation of Noise-Margin-Enhanced and Low-Power Memory Techniques for SoC Applications

A new memory design with a simple six-transistor memory cell achieves an enhanced read static noise margin. Based on using “pre-equalize” rather than “pre-charge” at the beginning of a read operation, the cross-coupled inverters of the memory cell have a switching threshold close to that of the conventional CMOS inverter circuit, thus achieving both compactness and increased data stability. The proposed can also potentially dramatically decrease power dissipation in conventional memory counterparts. Both simulations and measurements were carried out as proof of concept. The proposed memory hardware techniques are simple to implement and highly practical, making it quite competitive with other currently used methods.