Investigation of Noise-Margin-Enhanced and Low-Power Memory Techniques for SoC Applications

Cihun Siyong Alex Gong*

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

1 Scopus citations


A new memory design with a simple six-transistor memory cell achieves an enhanced read static noise margin. Based on using “pre-equalize” rather than “pre-charge” at the beginning of a read operation, the cross-coupled inverters of the memory cell have a switching threshold close to that of the conventional CMOS inverter circuit, thus achieving both compactness and increased data stability. The proposed can also potentially dramatically decrease power dissipation in conventional memory counterparts. Both simulations and measurements were carried out as proof of concept. The proposed memory hardware techniques are simple to implement and highly practical, making it quite competitive with other currently used methods.

Original languageEnglish
Pages (from-to)1115-1128
Number of pages14
JournalCircuits, Systems, and Signal Processing
Issue number4
StatePublished - 04 2015

Bibliographical note

Publisher Copyright:
© 2014, Springer Science+Business Media New York.


  • Low power
  • Memory
  • Noise margin
  • Pre-charge
  • Read stability


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