@inproceedings{4f03f0d4deaa43e686172f8f9454a9a7,
title = "Lane recognition system implemented by a full hardware design",
abstract = "In order to get a right decision instead of human eye, machine vision becomes a popular issue especially in the application field of automotive. This design provides a high speed lane recognition based on Terasic DE2-70 FPGA platform which included 4.3' touch LCD and a 500 Megapixel CCD camera. With full hardware design, this system can easily reduce the image processing and recognition time. The system with a relatively high rate of successful recognition under the 160 Km/hr can be achieved.",
keywords = "FPGA, Hardware design, Lane recognition system",
author = "Kang, {Pin Yang} and Chen, {Yen Po} and Jeng, {Ming Jer}",
year = "2014",
doi = "10.1109/ISNE.2014.6839353",
language = "英语",
isbn = "9781479947805",
series = "2014 International Symposium on Next-Generation Electronics, ISNE 2014",
publisher = "IEEE Computer Society",
booktitle = "2014 International Symposium on Next-Generation Electronics, ISNE 2014",
address = "美国",
note = "3rd International Symposium on Next-Generation Electronics, ISNE 2014 ; Conference date: 07-05-2014 Through 10-05-2014",
}