Lane recognition system implemented by a full hardware design

Pin Yang Kang, Yen Po Chen, Ming Jer Jeng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In order to get a right decision instead of human eye, machine vision becomes a popular issue especially in the application field of automotive. This design provides a high speed lane recognition based on Terasic DE2-70 FPGA platform which included 4.3' touch LCD and a 500 Megapixel CCD camera. With full hardware design, this system can easily reduce the image processing and recognition time. The system with a relatively high rate of successful recognition under the 160 Km/hr can be achieved.

Original languageEnglish
Title of host publication2014 International Symposium on Next-Generation Electronics, ISNE 2014
PublisherIEEE Computer Society
ISBN (Print)9781479947805
DOIs
StatePublished - 2014
Event3rd International Symposium on Next-Generation Electronics, ISNE 2014 - Taoyuan, Taiwan
Duration: 07 05 201410 05 2014

Publication series

Name2014 International Symposium on Next-Generation Electronics, ISNE 2014

Conference

Conference3rd International Symposium on Next-Generation Electronics, ISNE 2014
Country/TerritoryTaiwan
CityTaoyuan
Period07/05/1410/05/14

Keywords

  • FPGA
  • Hardware design
  • Lane recognition system

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