Latency-aware task scheduling on big.LITTLE heterogeneous computing architecture

Hsiao Chuan Chang, Zhi Ying Huang, Che Wei Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

To address the demands of lower energy consumption and higher computing performance, big.LITTLE architecture consisting of high-performance big cores and energy-efficient little cores has been proposed to provide a heterogeneous computing environment for balancing the needs of energy saving and performance improvement. For advanced big.LITTLE platforms, big and little cores can be active simultaneously and are exposed to the kernel scheduler, i.e., the operating system can assign tasks onto any cores. Based on the Linux kernel, Android adopts a heterogeneous multi-processing architecture to assign tasks with higher CPU utilization to big cores, and other tasks can be assigned to little cores so as to maintain the balanced utilization among all cores. However, there could be some tasks with very low utilization, but their response time is critical, e.g., user interfaces, interactive threads, and system monitoring threads. In this work, latency constraints are explicitly assigned to some critical tasks. We then leverage the original Android scheduler for keeping the utilization of all cores balanced and append our kernel module to the scheduler for estimating the latency of each thread and for scheduling all tasks with considerations of their latency constraints. Latency-critical tasks are then scheduled onto cores with latency guarantees, and other tasks can be scheduled for managing the workload balance of the system.

Original languageEnglish
Title of host publicationProceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018
EditorsArtde Donald Kin-Tak Lam, Stephen D. Prior, Teen-Hang Meen
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-14
Number of pages2
ISBN (Electronic)9781538643426
DOIs
StatePublished - 22 06 2018
Event4th IEEE International Conference on Applied System Innovation, ICASI 2018 - Chiba, Japan
Duration: 13 04 201817 04 2018

Publication series

NameProceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018

Conference

Conference4th IEEE International Conference on Applied System Innovation, ICASI 2018
Country/TerritoryJapan
CityChiba
Period13/04/1817/04/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

  • big.LITTL architecture
  • energy saving
  • latency-aware task scheduling
  • load balance

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