LDPC coded modulation for TLC flash memory

Huang Chang Lee, Jieng Heng Shy, Yen Ming Chen, Yeong Luh Ueng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

In this paper, a coded modulation scheme using extremely sparse low-density parity-check (LDPC) codes is proposed for the stored signal of triple-level-cell (TLC) NAND flash, where both the encoding and the decoding complexity can be significantly reduced with the advantage of the extremely sparse code graph. In order to enhance the performance of decoder, iterative detection decoding (IDD) is introduced to extract the extrinsic information from the symbol detector, and the cooperative non-Gray mapping is also designed. In addition, for error floor lowering, an interleaver is inserted to ensure the cascaded degree-2 variable nodes are separated to individual symbols. The simulation results show that the proposed coded modulation scheme can provide a practical error floor performance with a low decoding complexity.

Original languageEnglish
Title of host publication2017 IEEE Information Theory Workshop, ITW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages204-208
Number of pages5
ISBN (Electronic)9781509030972
DOIs
StatePublished - 02 07 2017
Event2017 IEEE Information Theory Workshop, ITW 2017 - Kaohsiung, Taiwan
Duration: 06 11 201710 11 2017

Publication series

NameIEEE International Symposium on Information Theory - Proceedings
Volume2018-January
ISSN (Print)2157-8095

Conference

Conference2017 IEEE Information Theory Workshop, ITW 2017
Country/TerritoryTaiwan
CityKaohsiung
Period06/11/1710/11/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

  • Coded modulation
  • LDPC codes
  • TLC flash memory

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