Lifetime modeling for stress-induced voiding in integrated circuit interconnections

By considering the stress-induced voiding (SIV) as a result of strain energy relief in the presence of flaws, an analytical lifetime model for SIV is derived from the energy perspective. The SIV lifetime is strongly dependent on the passivation integrity of the cap layer, effective bulk modulus of the interconnect system, diffusivities of the interconnect atoms in the dominant diffusion paths, stress free temperature, and temperature of the interconnection. The calculated SIV lifetime and the critical temperature are found to be consistent with the experimental values.