Low-complexity bit-parallel systolic architecture for computing AB2 + C in a class of finite field GF(2m)

Chiou Yng Lee; Erl Huei Lu; Lir Fang Sun

doi:10.1109/82.938363

Low-complexity bit-parallel systolic architecture for computing AB² + C in a class of finite field GF(2^m)

Chiou Yng Lee^*, Erl Huei Lu, Lir Fang Sun

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Journal Article › peer-review

32 Scopus citations

Abstract

An algorithm for computing AB² + C over a finite field GF(2^m) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems.

Original language	English
Pages (from-to)	519-523
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	48
Issue number	5
DOIs	https://doi.org/10.1109/82.938363
State	Published - 05 2001

Keywords

All one polynomial (AOP)
Finite field
Latency
Systolic multiplier

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10.1109/82.938363

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abstract = "An algorithm for computing AB2 + C over a finite field GF(2m) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems.",

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KW - Latency

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Low-complexity bit-parallel systolic architecture for computing AB² + C in a class of finite field GF(2^m)

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Keywords

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