Low-complexity bit-parallel systolic multipliers over GF(2m)

Chiou Yng Lee; Chin Chin Chen; Yuan Ho Chen; Erl Huei Lu

doi:10.1109/ICSMC.2006.384557

Low-complexity bit-parallel systolic multipliers over GF(2^m)

Chiou Yng Lee^*, Chin Chin Chen, Yuan Ho Chen, Erl Huei Lu

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2 ^m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.

Original language	English
Title of host publication	2006 IEEE International Conference on Systems, Man and Cybernetics
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1160-1165
Number of pages	6
ISBN (Print)	1424401003, 9781424401000
DOIs	https://doi.org/10.1109/ICSMC.2006.384557
State	Published - 2006
Event	2006 IEEE International Conference on Systems, Man and Cybernetics - Taipei, Taiwan Duration: 08 10 2006 → 11 10 2006

Publication series

Name	Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
Volume	2
ISSN (Print)	1062-922X

Conference

Conference	2006 IEEE International Conference on Systems, Man and Cybernetics
Country/Territory	Taiwan
City	Taipei
Period	08/10/06 → 11/10/06

Keywords

Folded technique
Interleaved conventional multiplication
Primitive polynomial
Systolic array

Access to Document

10.1109/ICSMC.2006.384557

Cite this

Lee, C. Y., Chen, C. C., Chen, Y. H., & Lu, E. H. (2006). Low-complexity bit-parallel systolic multipliers over GF(2^m). In 2006 IEEE International Conference on Systems, Man and Cybernetics (pp. 1160-1165). Article 4274005 (Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSMC.2006.384557

@inproceedings{42b394f90ec94702a62074a57247a146,

title = "Low-complexity bit-parallel systolic multipliers over GF(2m)",

abstract = "Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2 m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38\% and 54\% space complexity as compared to the traditional multipliers, respectively.",

keywords = "Folded technique, Interleaved conventional multiplication, Primitive polynomial, Systolic array",

author = "Lee, \{Chiou Yng\} and Chen, \{Chin Chin\} and Chen, \{Yuan Ho\} and Lu, \{Erl Huei\}",

year = "2006",

doi = "10.1109/ICSMC.2006.384557",

language = "英语",

isbn = "1424401003",

series = "Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1160--1165",

booktitle = "2006 IEEE International Conference on Systems, Man and Cybernetics",

address = "美国",

note = "2006 IEEE International Conference on Systems, Man and Cybernetics ; Conference date: 08-10-2006 Through 11-10-2006",

}

Lee, CY, Chen, CC, Chen, YH & Lu, EH 2006, Low-complexity bit-parallel systolic multipliers over GF(2^m). in 2006 IEEE International Conference on Systems, Man and Cybernetics., 4274005, Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1160-1165, 2006 IEEE International Conference on Systems, Man and Cybernetics, Taipei, Taiwan, 08/10/06. https://doi.org/10.1109/ICSMC.2006.384557

Low-complexity bit-parallel systolic multipliers over GF(2^m). / Lee, Chiou Yng; Chen, Chin Chin; Chen, Yuan Ho et al.
2006 IEEE International Conference on Systems, Man and Cybernetics. Institute of Electrical and Electronics Engineers Inc., 2006. p. 1160-1165 4274005 (Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Chiou Yng

AU - Chen, Chin Chin

AU - Chen, Yuan Ho

AU - Lu, Erl Huei

PY - 2006

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N2 - Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2 m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.

AB - Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2 m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.

KW - Folded technique

KW - Interleaved conventional multiplication

KW - Primitive polynomial

KW - Systolic array

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PB - Institute of Electrical and Electronics Engineers Inc.

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Lee CY, Chen CC, Chen YH, Lu EH. Low-complexity bit-parallel systolic multipliers over GF(2^m). In 2006 IEEE International Conference on Systems, Man and Cybernetics. Institute of Electrical and Electronics Engineers Inc. 2006. p. 1160-1165. 4274005. (Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics). doi: 10.1109/ICSMC.2006.384557