Low-complexity systolic multiplier over GF(2m) using weakly dual basis

Chiou Yng Lee; Ya Cheng Lu; Erl Huei Lu

doi:10.1109/APCCAS.2002.1114972

Low-complexity systolic multiplier over GF(2^m) using weakly dual basis

Chiou Yng Lee, Ya Cheng Lu, Erl Huei Lu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper offers a new bit-parallel systolic multiplier for GF(2^m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m² cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log₂m] clock cycles.

Original language	English
Title of host publication	Proceedings - APCCAS 2002
Subtitle of host publication	Asia-Pacific Conference on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	367-372
Number of pages	6
ISBN (Electronic)	0780376900
DOIs	https://doi.org/10.1109/APCCAS.2002.1114972
State	Published - 2002
Event	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia Duration: 28 10 2002 → 31 10 2002

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume	1

Conference

Conference	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Country/Territory	Indonesia
City	Denpasar, Bali
Period	28/10/02 → 31/10/02

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

Keywords

Arithmetic
Circuits
Clocks
Computer architecture
Concurrent computing
Cryptography
Delay
Error correction codes
Galois fields
Polynomials

Access to Document

10.1109/APCCAS.2002.1114972

Cite this

Lee, C. Y., Lu, Y. C., & Lu, E. H. (2002). Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (pp. 367-372). Article 1114972 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1114972

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abstract = "This paper offers a new bit-parallel systolic multiplier for GF(2m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m2 cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log2m] clock cycles.",

keywords = "Arithmetic, Circuits, Clocks, Computer architecture, Concurrent computing, Cryptography, Delay, Error correction codes, Galois fields, Polynomials",

author = "Lee, {Chiou Yng} and Lu, {Ya Cheng} and Lu, {Erl Huei}",

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year = "2002",

doi = "10.1109/APCCAS.2002.1114972",

language = "英语",

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Lee, CY, Lu, YC & Lu, EH 2002, Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1114972, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 367-372, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 28/10/02. https://doi.org/10.1109/APCCAS.2002.1114972

Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. / Lee, Chiou Yng; Lu, Ya Cheng; Lu, Erl Huei.
Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 367-372 1114972 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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KW - Circuits

KW - Clocks

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KW - Concurrent computing

KW - Cryptography

KW - Delay

KW - Error correction codes

KW - Galois fields

KW - Polynomials

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