Low-cost video transform for HEVC

Chieh Yang Liu, Wen Quan He, Yung Ming Chang, Yuan Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.

Original languageEnglish
Title of host publicationICIST 2014 - Proceedings of 2014 4th IEEE International Conference on Information Science and Technology
EditorsGuoqing Xu, Yu Qiao, Xinyu Wu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages221-224
Number of pages4
ISBN (Electronic)9781479948086
DOIs
StatePublished - 10 10 2014
Externally publishedYes
Event2014 4th IEEE International Conference on Information Science and Technology, ICIST 2014 - Shenzhen, China
Duration: 26 04 201428 04 2014

Publication series

NameICIST 2014 - Proceedings of 2014 4th IEEE International Conference on Information Science and Technology

Conference

Conference2014 4th IEEE International Conference on Information Science and Technology, ICIST 2014
Country/TerritoryChina
CityShenzhen
Period26/04/1428/04/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

  • High Efficiency Video Coding (HEVC)
  • Inverse discrete cosine transform (IDCT)
  • integer DCT
  • video coding

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