Abstract
In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.
Original language | English |
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Title of host publication | ICIST 2014 - Proceedings of 2014 4th IEEE International Conference on Information Science and Technology |
Editors | Guoqing Xu, Yu Qiao, Xinyu Wu |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 221-224 |
Number of pages | 4 |
ISBN (Electronic) | 9781479948086 |
DOIs | |
State | Published - 10 10 2014 |
Externally published | Yes |
Event | 2014 4th IEEE International Conference on Information Science and Technology, ICIST 2014 - Shenzhen, China Duration: 26 04 2014 → 28 04 2014 |
Publication series
Name | ICIST 2014 - Proceedings of 2014 4th IEEE International Conference on Information Science and Technology |
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Conference
Conference | 2014 4th IEEE International Conference on Information Science and Technology, ICIST 2014 |
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Country/Territory | China |
City | Shenzhen |
Period | 26/04/14 → 28/04/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
Keywords
- High Efficiency Video Coding (HEVC)
- Inverse discrete cosine transform (IDCT)
- integer DCT
- video coding