Low-error and area-efficient fixed-width multiplier by using fixed compensation circuit

In this paper, we propose a new error compensation circuit to lower input correction vector compensation error. To improve the error compensation precision, we restrict the compensation term between β and β-1 to remove the less-compensation situations. To reduce the hardware complexity in the error compensation circuit, we construct the error compensation circuit merely by the "outer" partial products. In this way, the hardware complexity can be lower and fixed as the multiplication operands width increase. As compared with the direct-truncated multiplier, the truncation error in the proposed 16×16 bit fixed-width multiplier can be lowered 86%. As compared with the complete full-length multiplier, the proposed fixed-width multiplier only demands 53% transistor counts. As compared with the state-of-art design, the proposed fixed-width multiplier not only performs with lower compensation error but also with lower hardware complexity, especially as multiplier input bits increase.