Low-error and area-efficient fixed-width multiplier by using minor input correction vector

I. Chyn Wey*, Chun Chien Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the "outer" partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.

Original languageEnglish
Title of host publicationICEIE 2010 - 2010 International Conference on Electronics and Information Engineering, Proceedings
PagesV1118-V1122
DOIs
StatePublished - 2010
Event2010 International Conference on Electronics and Information Engineering, ICEIE 2010 - Kyoto, Japan
Duration: 01 08 201003 08 2010

Publication series

NameICEIE 2010 - 2010 International Conference on Electronics and Information Engineering, Proceedings
Volume1

Conference

Conference2010 International Conference on Electronics and Information Engineering, ICEIE 2010
Country/TerritoryJapan
CityKyoto
Period01/08/1003/08/10

Keywords

  • Area-efficient
  • Fixed-width multiplier
  • Low-error
  • Minor input correction vector

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