Low-latency and power-efficient row-based binary-weighted compensator for fixed-width Booth multiplier

Fixed-width Booth multiplier (FWBM) plays a significant role in the arouse of approximate computing (AC) field. In this paper, a row-based binary-weighted compensator (RBC) for fixed-width Booth multiplication is proposed. The derived binary-weighted close-form minimizes the conversion loss and hardware cost. With the proposed close-form, the partial product array can be reduced dramatically. Consequently, the compact FWBM with the proposed RBC not only shortens the critical path to at least 24% but also minimizes the power dissipation to at least 44%. Moreover, the proposed RBC outperforms the state-of-art with a maximum merit improvement of 39%. By implementing the proposed RBC-FWBM in the FIR filter, we manage to demonstrate the practicality of the proposed design with a significant reduction in power-dissipation and delay while maintaining high accuracy.