Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules

Jhao Ji Ye; You Gang Chen; I. Chyn Wey; An Yeu Wu

doi:10.1109/iscas.2007.378044

Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules

Jhao Ji Ye^*, You Gang Chen, I. Chyn Wey, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

Data transmission on multiple clock domains will face reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50%-83% of latency. It is implemented on standard-cell library by using TSMC 0.18um 1P6M CMOS technology.

Original language	English
Article number	4252773
Pages (from-to)	869-872
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/iscas.2007.378044
State	Published - 2007
Externally published	Yes
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 05 2007 → 30 05 2007

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10.1109/iscas.2007.378044

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@article{58ad3a3e46be4b53bf88a92c00a6a602,

title = "Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules",

abstract = "Data transmission on multiple clock domains will face reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50%-83% of latency. It is implemented on standard-cell library by using TSMC 0.18um 1P6M CMOS technology.",

author = "Ye, {Jhao Ji} and Chen, {You Gang} and Wey, {I. Chyn} and Wu, {An Yeu}",

year = "2007",

doi = "10.1109/iscas.2007.378044",

language = "英语",

pages = "869--872",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

}

TY - JOUR

T1 - Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules

AU - Ye, Jhao Ji

AU - Chen, You Gang

AU - Wey, I. Chyn

AU - Wu, An Yeu

PY - 2007

Y1 - 2007

N2 - Data transmission on multiple clock domains will face reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50%-83% of latency. It is implemented on standard-cell library by using TSMC 0.18um 1P6M CMOS technology.

AB - Data transmission on multiple clock domains will face reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50%-83% of latency. It is implemented on standard-cell library by using TSMC 0.18um 1P6M CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=34548843400&partnerID=8YFLogxK

U2 - 10.1109/iscas.2007.378044

DO - 10.1109/iscas.2007.378044

M3 - 会议文章

AN - SCOPUS:34548843400

SN - 0271-4310

SP - 869

EP - 872

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 4252773

T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules

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