Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design

I. Chyn Wey; Jia Feng Huang; Cihun Siyong Alex Gong; Shiang Wei Li; Chang Chieh Lin; Chih Yun Chien; Yu Fan Luo; Yu Hung Kuo; Meng Jung Chang; Chin Chih Hsu

doi:10.1109/ISBB.2015.7344957

Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design

I. Chyn Wey, Jia Feng Huang, Cihun Siyong Alex Gong, Shiang Wei Li, Chang Chieh Lin, Chih Yun Chien, Yu Fan Luo, Yu Hung Kuo, Meng Jung Chang, Chin Chih Hsu

Department of Electrical Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we review state-of-the-art low-voltage fault-tolerable logic techniques that are promising for medical implants. The paper also proposes a method to get the efficiency comparasion of computationnal time delay, power consumption, enrgy efficiency and progress variation of logic gates such as static, transmission gate, DCVSL, dynamic and pesudo in different temperature, time and variations so that the researchers can have a design reference for ultra low-power digital blocks of the implantable systems.

Original language	English
Title of host publication	4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	196-199
Number of pages	4
ISBN (Electronic)	9781467366090
DOIs	https://doi.org/10.1109/ISBB.2015.7344957
State	Published - 02 12 2015
Event	4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015 - Beijing, China Duration: 14 10 2015 → 17 10 2015

Publication series

Name	4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015

Conference

Conference	4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015
Country/Territory	China
City	Beijing
Period	14/10/15 → 17/10/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISBB.2015.7344957

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Wey, I. C., Huang, J. F., Gong, C. S. A., Li, S. W., Lin, C. C., Chien, C. Y., Luo, Y. F., Kuo, Y. H., Chang, M. J., & Hsu, C. C. (2015). Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design. In 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015 (pp. 196-199). Article 7344957 (4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISBB.2015.7344957

Wey, I. Chyn ; Huang, Jia Feng ; Gong, Cihun Siyong Alex et al. / Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design. 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 196-199 (4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015).

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title = "Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design",

abstract = "In this paper, we review state-of-the-art low-voltage fault-tolerable logic techniques that are promising for medical implants. The paper also proposes a method to get the efficiency comparasion of computationnal time delay, power consumption, enrgy efficiency and progress variation of logic gates such as static, transmission gate, DCVSL, dynamic and pesudo in different temperature, time and variations so that the researchers can have a design reference for ultra low-power digital blocks of the implantable systems.",

author = "Wey, {I. Chyn} and Huang, {Jia Feng} and Gong, {Cihun Siyong Alex} and Li, {Shiang Wei} and Lin, {Chang Chieh} and Chien, {Chih Yun} and Luo, {Yu Fan} and Kuo, {Yu Hung} and Chang, {Meng Jung} and Hsu, {Chin Chih}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015 ; Conference date: 14-10-2015 Through 17-10-2015",

year = "2015",

month = dec,

day = "2",

doi = "10.1109/ISBB.2015.7344957",

language = "英语",

series = "4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "196--199",

booktitle = "4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015",

address = "美国",

}

Wey, IC, Huang, JF, Gong, CSA, Li, SW, Lin, CC, Chien, CY, Luo, YF, Kuo, YH, Chang, MJ & Hsu, CC 2015, Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design. in 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015., 7344957, 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015, Institute of Electrical and Electronics Engineers Inc., pp. 196-199, 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015, Beijing, China, 14/10/15. https://doi.org/10.1109/ISBB.2015.7344957

Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design. / Wey, I. Chyn; Huang, Jia Feng; Gong, Cihun Siyong Alex et al.
4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 196-199 7344957 (4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lin, Chang Chieh

AU - Chien, Chih Yun

AU - Luo, Yu Fan

AU - Kuo, Yu Hung

AU - Chang, Meng Jung

AU - Hsu, Chin Chih

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AB - In this paper, we review state-of-the-art low-voltage fault-tolerable logic techniques that are promising for medical implants. The paper also proposes a method to get the efficiency comparasion of computationnal time delay, power consumption, enrgy efficiency and progress variation of logic gates such as static, transmission gate, DCVSL, dynamic and pesudo in different temperature, time and variations so that the researchers can have a design reference for ultra low-power digital blocks of the implantable systems.

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ER -

Wey IC, Huang JF, Gong CSA, Li SW, Lin CC, Chien CY et al. Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design. In 4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 196-199. 7344957. (4th International Symposium on Bioelectronics and Bioinformatics, ISBB 2015). doi: 10.1109/ISBB.2015.7344957

Low-power design towards implantable neural signal processor-energy efficiency analysis for near-threshold voltage circuits design

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