TY - GEN
T1 - Low power reversible variable length decoder for MPEG-4 based on fast codeword detection and table partition
AU - Lai, Yeong Kang
AU - Lai, Yu Fan
AU - Huang, Yin Ruey
PY - 2011
Y1 - 2011
N2 - Variable length coding (VLC) is a widely used technique in digital video compression systems. It is known for its efficient compression, but is susceptible to noisy environments. Due to the increased demand for multimedia systems to be portable, power consumption and power saving become important issues. Current ITU H.263+ and ISO MPEG-4 standards have used reversible variable length coding (RVLC) which provides greater error robustness than non-reversible counterparts (VLC) due to the growing need for wireless exchange of compressed image and video signals over noisy channels. In this paper, a new method for RVLC decoding is described. Since the special structure of RVLC codewords, the decoding techniques that are common for regular VLC are less efficient when used with RVLC. The new method uses simple logical operations to determine the length of codewords quickly, and then codewords are decoded. It is easily implemented with hardware. We propose a VLSI architecture based on this new method. The architecture also uses the technique of table partitioning. The experimental result shows that our architecture can achieve lower power consumption without sacrificing the quality of the performance. The proposed architecture has been implemented using standard cell methodology for TSMC 0.18um 1P6M technology. The chip implementation results show that proposed architecture can work at 100MHz and its power consumption is only 46.69 uW/MHz.
AB - Variable length coding (VLC) is a widely used technique in digital video compression systems. It is known for its efficient compression, but is susceptible to noisy environments. Due to the increased demand for multimedia systems to be portable, power consumption and power saving become important issues. Current ITU H.263+ and ISO MPEG-4 standards have used reversible variable length coding (RVLC) which provides greater error robustness than non-reversible counterparts (VLC) due to the growing need for wireless exchange of compressed image and video signals over noisy channels. In this paper, a new method for RVLC decoding is described. Since the special structure of RVLC codewords, the decoding techniques that are common for regular VLC are less efficient when used with RVLC. The new method uses simple logical operations to determine the length of codewords quickly, and then codewords are decoded. It is easily implemented with hardware. We propose a VLSI architecture based on this new method. The architecture also uses the technique of table partitioning. The experimental result shows that our architecture can achieve lower power consumption without sacrificing the quality of the performance. The proposed architecture has been implemented using standard cell methodology for TSMC 0.18um 1P6M technology. The chip implementation results show that proposed architecture can work at 100MHz and its power consumption is only 46.69 uW/MHz.
UR - http://www.scopus.com/inward/record.url?scp=80052394433&partnerID=8YFLogxK
U2 - 10.1109/ISCE.2011.5973907
DO - 10.1109/ISCE.2011.5973907
M3 - 会议稿件
AN - SCOPUS:80052394433
SN - 9781612848433
T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE
SP - 631
EP - 634
BT - ISCE 2011 - 15th IEEE International Symposium on Consumer Electronics
T2 - 15th IEEE International Symposium on Consumer Electronics, ISCE 2011
Y2 - 14 June 2011 through 17 June 2011
ER -