TY - GEN
T1 - Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications
AU - Chen, Lien Fei
AU - Huang, Tai Lun
AU - Lai, Yeong Kang
PY - 2005
Y1 - 2005
N2 - In this paper, a cost effective bit-plane coder with throughput enhancement in JPEG2000 applications is proposed. Many literatures and the results of the chip implementation show that the memory requirement dominates the hardware cost of the bit-plane coder. In order to reduce the memory size, the memory-free algorithm is proposed to eliminate state variable memories by calculating three coding state variables (γp+1[n], σp+1[n], and πp[n]) on the fly. Moreover, we also propose the stripe-column-based pass-parallel operation to perform three coding passes in pipeline operation and to encode four samples within the stripe-column concurrently for the high throughput requirement. The experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures because of the proposed memory-free algorithm. Furthermore, the proposed architecture has 3 times greater throughput than other familiar architectures.
AB - In this paper, a cost effective bit-plane coder with throughput enhancement in JPEG2000 applications is proposed. Many literatures and the results of the chip implementation show that the memory requirement dominates the hardware cost of the bit-plane coder. In order to reduce the memory size, the memory-free algorithm is proposed to eliminate state variable memories by calculating three coding state variables (γp+1[n], σp+1[n], and πp[n]) on the fly. Moreover, we also propose the stripe-column-based pass-parallel operation to perform three coding passes in pipeline operation and to encode four samples within the stripe-column concurrently for the high throughput requirement. The experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures because of the proposed memory-free algorithm. Furthermore, the proposed architecture has 3 times greater throughput than other familiar architectures.
UR - http://www.scopus.com/inward/record.url?scp=33646762859&partnerID=8YFLogxK
U2 - 10.1109/ICASSP.2005.1416229
DO - 10.1109/ICASSP.2005.1416229
M3 - 会议稿件
AN - SCOPUS:33646762859
SN - 0780388747
SN - 9780780388741
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - V17-V20
BT - 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05
Y2 - 18 March 2005 through 23 March 2005
ER -