Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification

H. C. Chow; W. S. Feng

doi:10.1049/el:19920731

Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification

H. C. Chow^*
, W. S. Feng

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

1 Scopus citations

Abstract

A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.

Original language	English
Pages (from-to)	1159-1160
Number of pages	2
Journal	Electronics Letters
Volume	28
Issue number	12
DOIs	https://doi.org/10.1049/el:19920731
State	Published - 04 06 1992
Externally published	Yes

Keywords

Field-effect transistors
Modelling

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10.1049/el:19920731

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title = "Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification",

abstract = "A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.",

keywords = "Field-effect transistors, Modelling",

author = "Chow, \{H. C.\} and Feng, \{W. S.\}",

year = "1992",

month = jun,

day = "4",

doi = "10.1049/el:19920731",

language = "英语",

volume = "28",

pages = "1159--1160",

journal = "Electronics Letters",

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AU - Feng, W. S.

PY - 1992/6/4

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N2 - A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.

AB - A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.

KW - Field-effect transistors

KW - Modelling

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U2 - 10.1049/el:19920731

DO - 10.1049/el:19920731

M3 - 文章

AN - SCOPUS:0027111574

SN - 0013-5194

VL - 28

SP - 1159

EP - 1160

JO - Electronics Letters

JF - Electronics Letters

IS - 12

ER -

Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification

Abstract

Keywords

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