Modeling and analysis of gate-all-around silicon nanowire FET

Xiangchen Chen; Cher Ming Tan

doi:10.1016/j.microrel.2013.12.009

Modeling and analysis of gate-all-around silicon nanowire FET

Xiangchen Chen^*
, Cher Ming Tan

^*Corresponding author for this work

Nanyang Technological University

Research output: Contribution to journal › Journal Article › peer-review

38 Scopus citations

Abstract

In this paper, we report the TCAD study on gate-all-around (GAA) silicon nanowire (SiNW) FET. The device carrier transport physics, self-heating effect and process induced stress effect are discussed. With a comparison study between GAA SiNW FET and FinFET, the advantages of GAA SiNW FET on gate controllability and short channel effect immunity are evaluated.

Original language	English
Pages (from-to)	1103-1108
Number of pages	6
Journal	Microelectronics Reliability
Volume	54
Issue number	6-7
DOIs	https://doi.org/10.1016/j.microrel.2013.12.009
State	Published - 2014
Externally published	Yes

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10.1016/j.microrel.2013.12.009

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title = "Modeling and analysis of gate-all-around silicon nanowire FET",

abstract = "In this paper, we report the TCAD study on gate-all-around (GAA) silicon nanowire (SiNW) FET. The device carrier transport physics, self-heating effect and process induced stress effect are discussed. With a comparison study between GAA SiNW FET and FinFET, the advantages of GAA SiNW FET on gate controllability and short channel effect immunity are evaluated.",

author = "Xiangchen Chen and Tan, \{Cher Ming\}",

year = "2014",

doi = "10.1016/j.microrel.2013.12.009",

language = "英语",

volume = "54",

pages = "1103--1108",

journal = "Microelectronics Reliability",

issn = "0026-2714",

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number = "6-7",

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TY - JOUR

T1 - Modeling and analysis of gate-all-around silicon nanowire FET

AU - Chen, Xiangchen

AU - Tan, Cher Ming

PY - 2014

Y1 - 2014

N2 - In this paper, we report the TCAD study on gate-all-around (GAA) silicon nanowire (SiNW) FET. The device carrier transport physics, self-heating effect and process induced stress effect are discussed. With a comparison study between GAA SiNW FET and FinFET, the advantages of GAA SiNW FET on gate controllability and short channel effect immunity are evaluated.

AB - In this paper, we report the TCAD study on gate-all-around (GAA) silicon nanowire (SiNW) FET. The device carrier transport physics, self-heating effect and process induced stress effect are discussed. With a comparison study between GAA SiNW FET and FinFET, the advantages of GAA SiNW FET on gate controllability and short channel effect immunity are evaluated.

UR - https://www.scopus.com/pages/publications/84901620874

U2 - 10.1016/j.microrel.2013.12.009

DO - 10.1016/j.microrel.2013.12.009

M3 - 文章

AN - SCOPUS:84901620874

SN - 0026-2714

VL - 54

SP - 1103

EP - 1108

JO - Microelectronics Reliability

JF - Microelectronics Reliability

IS - 6-7

ER -

Modeling and analysis of gate-all-around silicon nanowire FET

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