Monolayer MoS2 for nonvolatile memory applications

Kai Ping Chang; Jer Chyi Wang; Chang Hsiao Chen; Lain Jong Li; Chao Sung Lai

doi:10.1109/ICSICT.2016.7998959

Monolayer MoS₂ for nonvolatile memory applications

Kai Ping Chang
, Jer Chyi Wang
, Chang Hsiao Chen
, Lain Jong Li
, Chao Sung Lai

Department of Electronic Engineering

Chang Gung University
Chang Gung Memorial Hospital
Feng Chia University
Academia Sinica - Institute of Atomic and Molecular Sciences
Ming Chi University of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this work, two-dimensional MoS2 has been performed for nonvolatile memory application as charge storage layer. The capacitance-voltage (C-V) hysteresis and programming characteristics of MoS2-NVMs with blocking oxide layer of various thicknesses have been further investigated. The MoS2-NVMs with 9-nm-thck blocking oxide layer exhibits a large hysteresis in the C-V sweeping and the fastest speed in programming characteristics. In addition, both electrons and holes can store in MoS2 monolayer, contributing to a promising application in future high-performance NVMs.

Original language	English
Title of host publication	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings
Editors	Yu-Long Jiang, Ting-Ao Tang, Ru Huang
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	489-491
Number of pages	3
ISBN (Electronic)	9781467397179
DOIs	https://doi.org/10.1109/ICSICT.2016.7998959
State	Published - 2016
Event	13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China Duration: 25 10 2016 → 28 10 2016

Publication series

Name	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

Conference

Conference	13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016
Country/Territory	China
City	Hangzhou
Period	25/10/16 → 28/10/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Access to Document

10.1109/ICSICT.2016.7998959

Cite this

Chang, K. P., Wang, J. C., Chen, C. H., Li, L. J., & Lai, C. S. (2016). Monolayer MoS₂ for nonvolatile memory applications. In Y.-L. Jiang, T.-A. Tang, & R. Huang (Eds.), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings (pp. 489-491). Article 7998959 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2016.7998959

Chang, Kai Ping ; Wang, Jer Chyi ; Chen, Chang Hsiao et al. / Monolayer MoS₂ for nonvolatile memory applications. 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. editor / Yu-Long Jiang ; Ting-Ao Tang ; Ru Huang. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 489-491 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings).

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title = "Monolayer MoS2 for nonvolatile memory applications",

abstract = "In this work, two-dimensional MoS2 has been performed for nonvolatile memory application as charge storage layer. The capacitance-voltage (C-V) hysteresis and programming characteristics of MoS2-NVMs with blocking oxide layer of various thicknesses have been further investigated. The MoS2-NVMs with 9-nm-thck blocking oxide layer exhibits a large hysteresis in the C-V sweeping and the fastest speed in programming characteristics. In addition, both electrons and holes can store in MoS2 monolayer, contributing to a promising application in future high-performance NVMs.",

author = "Chang, \{Kai Ping\} and Wang, \{Jer Chyi\} and Chen, \{Chang Hsiao\} and Li, \{Lain Jong\} and Lai, \{Chao Sung\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 ; Conference date: 25-10-2016 Through 28-10-2016",

year = "2016",

doi = "10.1109/ICSICT.2016.7998959",

language = "英语",

series = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "489--491",

editor = "Yu-Long Jiang and Ting-Ao Tang and Ru Huang",

booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",

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}

Chang, KP, Wang, JC, Chen, CH, Li, LJ & Lai, CS 2016, Monolayer MoS₂ for nonvolatile memory applications. in Y-L Jiang, T-A Tang & R Huang (eds), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings., 7998959, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 489-491, 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016, Hangzhou, China, 25/10/16. https://doi.org/10.1109/ICSICT.2016.7998959

Monolayer MoS₂ for nonvolatile memory applications. / Chang, Kai Ping; Wang, Jer Chyi; Chen, Chang Hsiao et al.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. ed. / Yu-Long Jiang; Ting-Ao Tang; Ru Huang. Institute of Electrical and Electronics Engineers Inc., 2016. p. 489-491 7998959 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Wang, Jer Chyi

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PY - 2016

Y1 - 2016

N2 - In this work, two-dimensional MoS2 has been performed for nonvolatile memory application as charge storage layer. The capacitance-voltage (C-V) hysteresis and programming characteristics of MoS2-NVMs with blocking oxide layer of various thicknesses have been further investigated. The MoS2-NVMs with 9-nm-thck blocking oxide layer exhibits a large hysteresis in the C-V sweeping and the fastest speed in programming characteristics. In addition, both electrons and holes can store in MoS2 monolayer, contributing to a promising application in future high-performance NVMs.

AB - In this work, two-dimensional MoS2 has been performed for nonvolatile memory application as charge storage layer. The capacitance-voltage (C-V) hysteresis and programming characteristics of MoS2-NVMs with blocking oxide layer of various thicknesses have been further investigated. The MoS2-NVMs with 9-nm-thck blocking oxide layer exhibits a large hysteresis in the C-V sweeping and the fastest speed in programming characteristics. In addition, both electrons and holes can store in MoS2 monolayer, contributing to a promising application in future high-performance NVMs.

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A2 - Jiang, Yu-Long

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PB - Institute of Electrical and Electronics Engineers Inc.

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Chang KP, Wang JC, Chen CH, Li LJ, Lai CS. Monolayer MoS₂ for nonvolatile memory applications. In Jiang YL, Tang TA, Huang R, editors, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. p. 489-491. 7998959. (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings). doi: 10.1109/ICSICT.2016.7998959