MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

W. C. Lin; H. P. Huang; K. H. Kao; M. H. Chiang; D. Lu; W. C. Hsu; Y. H. Wang; W. C.Y. Ma; H. H. Tsai; Y. J. Lee; H. L. Chiang; J. F. Wang; I. Radu

doi:10.1109/ESSDERC59256.2023.10268514

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

W. C. Lin, H. P. Huang, K. H. Kao, M. H. Chiang, D. Lu, W. C. Hsu, Y. H. Wang, W. C.Y. Ma, H. H. Tsai, Y. J. Lee, H. L. Chiang, J. F. Wang, I. Radu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

Original language	English
Title of host publication	ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference
Publisher	Editions Frontieres
Pages	9-12
Number of pages	4
ISBN (Electronic)	9798350304237
DOIs	https://doi.org/10.1109/ESSDERC59256.2023.10268514
State	Published - 2023
Externally published	Yes
Event	53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 - Lisbon, Portugal Duration: 11 09 2023 → 14 09 2023

Publication series

Name	European Solid-State Device Research Conference
Volume	2023-September
ISSN (Print)	1930-8876

Conference

Conference	53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023
Country/Territory	Portugal
City	Lisbon
Period	11/09/23 → 14/09/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

MOSFET
subthreshold swing
supply voltage

Access to Document

10.1109/ESSDERC59256.2023.10268514

Cite this

Lin, W. C., Huang, H. P., Kao, K. H., Chiang, M. H., Lu, D., Hsu, W. C., Wang, Y. H., Ma, W. C. Y., Tsai, H. H., Lee, Y. J., Chiang, H. L., Wang, J. F., & Radu, I. (2023). MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. In ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (pp. 9-12). (European Solid-State Device Research Conference; Vol. 2023-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC59256.2023.10268514

@inproceedings{94285809286e4ab4ae4d14129a20ab76,

title = "MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization",

abstract = "Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.",

keywords = "MOSFET, subthreshold swing, supply voltage",

author = "Lin, {W. C.} and Huang, {H. P.} and Kao, {K. H.} and Chiang, {M. H.} and D. Lu and Hsu, {W. C.} and Wang, {Y. H.} and Ma, {W. C.Y.} and Tsai, {H. H.} and Lee, {Y. J.} and Chiang, {H. L.} and Wang, {J. F.} and I. Radu",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",

year = "2023",

doi = "10.1109/ESSDERC59256.2023.10268514",

language = "英语",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

pages = "9--12",

booktitle = "ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference",

}

Lin, WC, Huang, HP, Kao, KH, Chiang, MH, Lu, D, Hsu, WC, Wang, YH, Ma, WCY, Tsai, HH, Lee, YJ, Chiang, HL, Wang, JF & Radu, I 2023, MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. in ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. European Solid-State Device Research Conference, vol. 2023-September, Editions Frontieres, pp. 9-12, 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, 11/09/23. https://doi.org/10.1109/ESSDERC59256.2023.10268514

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. / Lin, W. C.; Huang, H. P.; Kao, K. H. et al.
ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. Editions Frontieres, 2023. p. 9-12 (European Solid-State Device Research Conference; Vol. 2023-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

AU - Lin, W. C.

AU - Huang, H. P.

AU - Kao, K. H.

AU - Chiang, M. H.

AU - Lu, D.

AU - Hsu, W. C.

AU - Wang, Y. H.

AU - Ma, W. C.Y.

AU - Tsai, H. H.

AU - Lee, Y. J.

AU - Chiang, H. L.

AU - Wang, J. F.

AU - Radu, I.

PY - 2023

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N2 - Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

AB - Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

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KW - supply voltage

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ER -

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

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Keywords

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