Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

Herng Jer Lee; Chia Chi Chu; Wu Shiung Feng

Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

Herng Jer Lee^*, Chia Chi Chu, Wu Shiung Feng

^*Corresponding author for this work

Chang Gung University

Research output: Contribution to conference › Conference Paper › peer-review

7 Scopus citations

Abstract

This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

Original language	English
Pages	1009-1012
Number of pages	4
State	Published - 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 06 12 2004 → 09 12 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	06/12/04 → 09/12/04

Cite this

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title = "Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)",

abstract = "This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Pad{\'e} approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.",

author = "Lee, {Herng Jer} and Chu, {Chia Chi} and Feng, {Wu Shiung}",

year = "2004",

language = "英语",

pages = "1009--1012",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

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Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO). / Lee, Herng Jer; Chu, Chia Chi; Feng, Wu Shiung.
2004. 1009-1012 Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

Research output: Contribution to conference › Conference Paper › peer-review

TY - CONF

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AU - Lee, Herng Jer

AU - Chu, Chia Chi

AU - Feng, Wu Shiung

PY - 2004

Y1 - 2004

N2 - This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

AB - This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

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M3 - 论文

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

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Conference

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