Multilayered image processing for multiscale harris corner detection in digital realization

Pei Yung Hsiao*, Chieh Lun Lu, Li Chen Fu

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

57 Scopus citations

Abstract

The PC-based software programming used in complex or luxuriant image processing algorithms is time consuming and resource wasting. As appropriate processing for the image data indeed speedups complicated algorithms, we focus on a crucial casemultilayered processes. In this paper, we gauge deeply into the data flow of multilayered image processing to avoid waiting for the result from every previous steps to access the memory which occurs in many applicable algorithms. Based on combining the parallel and pipelined properties to eliminate unnecessary delays, we propose new visual pipeline architecture and use field programmable gate array to implement our hardware scheme. For verification, the multiscale Harris corner detector in cooperating with shape context and thin-plate splines were combined to complete our real-time experiment of the integrated hardware and software (H/S) system for pattern recognition.

Original languageEnglish
Article number5409580
Pages (from-to)1799-1805
Number of pages7
JournalIEEE Transactions on Industrial Electronics
Volume57
Issue number5
DOIs
StatePublished - 05 2010
Externally publishedYes

Keywords

  • Field-programmable gate array (FPGA)
  • Multilayered image processing
  • Multiscale Harris corner detection
  • Pattern recognition

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