Negative bias temperature instability for sputtering modification in a TiN diffusion barrier of p⁺ polysilicon gate stack in 50-nm DRAM technology

Negative bias temperature instability (NBTI) in plasma-nitrided oxide affected by the nitrogen incorporation of a TiN diffusion barrier layer of gate stack is first proposed. In the standard 50-nm DRAM technology, three different groups including high, medium, and low N₂ flow were deposited by sputtering to investigate in this paper. The high N₂ flow group was with higher drive current and higher transconductance, but worse NBTI performance in pMOSFETs than that of the low N₂ flow group. Boron (B) concentration at the bottom of p⁺ polycrystalline silicon (poly-Si) for the high N₂ flow group is 5.4% higher than that for the low N₂ flow group, which is verified by the secondary ion mass spectroscopy depth profile. A vertical electric field across gate nitrided oxide enhanced by high B concentration in the interface of p⁺ poly-Si/nitrided oxide resulted in the degradation of NBTI and time-dependent dielectric breakdown of the high N₂ flow group. However, process optimization still needs to be studied between device performance and reliability of pMOSFETs in future generation.