New bit-parallel systolic multipliers for a class of GF(2m)

Chiou Yng Lee; Erl Huei Lu; Jau Yien Lee

doi:10.1109/ISCAS.2001.922303

New bit-parallel systolic multipliers for a class of GF(2^m)

Chiou Yng Lee
, Erl Huei Lu
, Jau Yien Lee

Department of Electrical Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The operations of the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplications over a class of GF(2/sup m/) was developed in this paper. The low complexity bit-parallel systolic multiplier is presented. The multiplier has very low latency, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplications over the class of GF(2/sup m/) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	578-581
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922303
State	Published - 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 06 05 2001 → 09 05 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	06/05/01 → 09/05/01

Access to Document

10.1109/ISCAS.2001.922303

Cite this

Lee, C. Y., Lu, E. H., & Lee, J. Y. (2001). New bit-parallel systolic multipliers for a class of GF(2^m). In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 578-581). Article 922303 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922303

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abstract = "The operations of the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplications over a class of GF(2/sup m/) was developed in this paper. The low complexity bit-parallel systolic multiplier is presented. The multiplier has very low latency, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplications over the class of GF(2/sup m/) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m.",

author = "Lee, \{Chiou Yng\} and Lu, \{Erl Huei\} and Lee, \{Jau Yien\}",

year = "2001",

doi = "10.1109/ISCAS.2001.922303",

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note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

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Lee, CY, Lu, EH & Lee, JY 2001, New bit-parallel systolic multipliers for a class of GF(2^m). in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922303, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 578-581, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 06/05/01. https://doi.org/10.1109/ISCAS.2001.922303

New bit-parallel systolic multipliers for a class of GF(2^m). / Lee, Chiou Yng; Lu, Erl Huei; Lee, Jau Yien.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 578-581 922303 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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