New symmetrical buffer design for VLSI applications

Novel fast buffers by the transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in their structure, therefore the design is straightforward and the well balanced speed can be easily obtained. As compared with prior work, the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer circuit shows 27% and 76% average speed enhancements on propagation delays with only 7.3% average increase in its power consumption.