TY - GEN
T1 - Novel C-testable design for H.264 Integer Motion Estimation
AU - Yeh, Po Yu
AU - Ye, Bo Yuan
AU - Kuo, Sy Yen
AU - Lu, Shyue Kung
PY - 2008
Y1 - 2008
N2 - H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for testing H.264-IME block, but the test time usually increases as the design grows. In this paper, a C-testable DFT (Design-for-Testability) scheme at bit-plane level is proposed by using the Iterative-Logic-Array (ILA) architecture for the largest part in H.264-IME block. A simple BIST (built-in self-test) circuit is also proposed due to the ILA architecture, and the number of test pattern (NTP), hardware overhead (HO) and delay-time overhead (DTO) are only about 192, 4.70% and 5.56% respectively. The proposed DFT scheme reduces the test time and test cost significantly.
AB - H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for testing H.264-IME block, but the test time usually increases as the design grows. In this paper, a C-testable DFT (Design-for-Testability) scheme at bit-plane level is proposed by using the Iterative-Logic-Array (ILA) architecture for the largest part in H.264-IME block. A simple BIST (built-in self-test) circuit is also proposed due to the ILA architecture, and the number of test pattern (NTP), hardware overhead (HO) and delay-time overhead (DTO) are only about 192, 4.70% and 5.56% respectively. The proposed DFT scheme reduces the test time and test cost significantly.
UR - https://www.scopus.com/pages/publications/63449084577
U2 - 10.1109/ICECE.2008.4769306
DO - 10.1109/ICECE.2008.4769306
M3 - 会议稿件
AN - SCOPUS:63449084577
SN - 9781424420155
T3 - Proceedings of ICECE 2008 - 5th International Conference on Electrical and Computer Engineering
SP - 735
EP - 740
BT - Proceedings of ICECE 2008 - 5th International Conference on Electrical and Computer Engineering
T2 - 5th International Conference on Electrical and Computer Engineering, ICECE 2008
Y2 - 20 December 2008 through 22 December 2008
ER -